Delay element circuits are widely used in analog and digital electronic circuitry. The purpose of such a circuit is to take an input signal, to delay it for a period of time, and to then pass the signal to an output circuit. Delay element circuits may be used to adjust the setup (ts) and hold (th) times of signals entering a circuit, or to adjust the clock to output time (sometimes referred to as tCO or tCQ) of signals leaving a circuit. Delay elements may also be used to adjust the timing of clock and data signals output from electronic devices, such as memory devices.
An embodiment of a conventional delay element circuit is shown in FIG. 1. This circuit 100 includes a first operational transconductance amplifier (OTA) 110, commonly referred to as an ‘op-amp’, and second OTA 115. This circuit 100 further includes a first resistor 120, a second resistor 125, a trip inverter 130, a delay inverter 135, and a first (M1), second (M2), third (M3), fourth (M4), fifth (M5), and sixth (M6) transistor. In the exemplary embodiment of FIG. 1, the second (M2), fifth (M5), and sixth (M6) transistors include NMOS transistors, and the first (M1), third (M3), and fourth (M4) transistors include PMOS transistors.
The delay element of the conventional implementation 100 includes the path from the input marked ‘in 140’, through the fourth (M4) and fifth (M5) transistors and through the delay inverter 135 to the output 150. The propagation delay time (Tpd) of a falling edge through this circuit is given by the following equation (1), where Cin 155 is the input capacitance of the delay inverter 135 as shown in FIG. 1, m is the multiplier of the transistor size (e.g., m=M3/M1), R is the value of the resistor, and vtrip is the trip voltage for the inverter:                                                                         Tpd                ⁢                                                                  ⁢                                  (                                      of                    ⁢                                                                                  ⁢                    a                    ⁢                                                                                  ⁢                    falling                    ⁢                                                                                  ⁢                    edge                                    )                                            =                              Cin                *                                                      (                                          vtrip                      -                      0                                        )                                    /                  m                                *                Ip                                                                                        =                              Cin                *                                                      (                    vtrip                    )                                    /                  m                                *                                  (                                      vtrip_p                    /                    R                                    )                                                                                                        =                              Cin                *                                  R                  /                  m                                ⁢                                                                  ⁢                                                      (                                          since                      ⁢                                                                                          ⁢                                              vtrip                        ~                        vtrip_p                                                              )                                    .                                                                                        (        1        )            The delay of a rising edge through this circuit is given by equation (2):                                                                         Tpd                ⁢                                                                  ⁢                                  (                                      of                    ⁢                                                                                  ⁢                    a                    ⁢                                                                                  ⁢                    rising                    ⁢                                                                                  ⁢                    edge                                    )                                            =                              Cin                *                                                      (                                          vdd                      -                      vtrip                                        )                                    /                  m                                *                In                                                                                        =                              Cin                *                                                      (                                          vdd                      -                      vtrip                                        )                                    /                  m                                *                                                      (                                          vdd                      -                      vtrip_n                                        )                                    /                  R                                                                                                        =                              Cin                *                                  R                  /                  m                                ⁢                                                                  ⁢                                                      (                                          since                      ⁢                                                                                          ⁢                                              vtrip                        ~                        vtrip_n                                                              )                                    .                                                                                        (        2        )            
The delay is a product of the first resistor 120 and the second resistor 125 values, marked ‘R’, and the input capacitance 155 of the delay inverter 135 as shown in FIG. 1. These resistor and capacitor values are fixed, and are typically chosen in the design phase to match the desired operating frequency of the circuit. However, these resistor and capacitor values will vary with process, voltage, and temperature (PVT), and as a result, the delay of circuit 100 will vary in response to PVT variations.
In one exemplary embodiment, simulations of this circuit show a plus or minus 37 percent variation in delay across PVT. A disadvantage of this conventional circuit 100 is that the wide variation in propagation delay across PVT may cause improper operation of the application. A further disadvantage of this conventional circuit 100 is that the propagation delay of this element (which depends only on the resistance and input capacitance values of the circuit), once designed, does not readily adjust in proportion to an input signal.